Requirements Needed in the Implementation of the Experiment
Two commercial SiC MOSFET power modules, Cree’s 1.2 kV/300 A and Rohm’s 1.2 kV/180 A, underwent a non-destructive testing (NDT) investigation at Aalborg University, Denmark. As shown in Figure 1, the NDT setup involved a high-voltage power supply charging a capacitor bank for testing up to 10 kA and 2.4 kV without device destruction. The system included protection switches, a computer-designed busbar for current distribution, and a 100 MHz FPGA for signal control and measurement acquisition. A PC facilitated data acquisition and remote control, linked to an oscilloscope and FPGA board. Cree's recommended gate driver, CGD15HB62P, was used with desaturation protection disabled. Experiments were conducted with gate-emitter voltages of +20 V/-6 V and a 5 Ω external gate resistance, ensuring proper controllability at a case temperature of approximately 25°C.
Figure 1: Schematic diagram of the non-destructive testing model.
On the other hand, for the software section, an automated tool with a user-friendly GUI in MATLAB helped in the short circuit testing, ensuring maximum consistency. Users input test parameters, including test quantity and pulse interval. The GUI then passes the conditions and initiates tests, communicating the sequence to the FPGA. A 30-second off-time permits device cooling between tests. Data checks prevent fatal errors during communication and a local echo displays parameters sent to the FPGA for user reference. Following each test, waveforms are acquired through Active-X functions from the oscilloscope, capturing test index and time-stamp data for storage. This system facilitates repetitive testing, providing a reliable method for assessing device performance while offering ease of use through its intuitive interface.
Results Obtained
A.1.2 kV/ 300 A SiC MOSFET:Figure 2 depicts a short-circuit event where a 1.2 kV/300 A SiC MOSFET fails in 3.2 μs at 600 V bias and 25°C. The device survived up to 3.1 μs but failed due to thermal runaway in the subsequent pulse. Initially, the drain current surged to 5 kA, then decreased, suggesting an internal temperature rise. Delayed failure occurred after 2 μs due to a burn-out chip and short circuit. Thermal runaway was attributed to a high off-state leakage current activating a parasitic BJT. Another failure mechanism observed involved a gate-source short circuit caused by local overheating, exacerbated by gate oxide issues. Higher voltages and temperatures intensified gate leakage. Addressing these concerns is crucial for SiC MOSFET reliability.
Figure 2:SiC MOSFET fails in 3.2 μs at 600 V bias and 25°C.
B.1.2 kV/ 180 A SiC MOSFET:Short circuit tests were conducted on a 1.2 kV/180 A SiC MOSFET from Rohm, resulting in failure within 7.2 μs at VDC = 800 V. A thermal runaway failure occurred after 7 μs despite the device initially turning off the short circuit current. Burn-out of one MOSFET chip was observed, with a progressively increasing current tail indicating high drain leakage. The calculated critical energy for the 1.2 kV/180 A device was 8.2 J. Compared to a 1.2 kV/300 A device, the 1.2 kV/180 A module exhibited higher robustness against short circuits due to its lower drain saturation current, resulting in better temperature stress handling. Critical short circuit energies were 6.9 J for the 1.2 kV/300 A device and 8.2 J for the 1.2 kV/180 A device, indicating the latter's superior capability to withstand higher temperature stress.
The Proposed System Based on Short-Circuit Criterion
The technique proposed shows a method to characterize the Short-Circuit Safe Operation Area (SCSOA) of SiC MOSFETs by monitoring short-circuit current and gate-source voltage. This method involves setting limits for these parameters based on two safety criteria. Experimental results show positive results in predicting short-circuit failures. The algorithm involves setting limits for short-circuit current (ID,SOA) and gate-source voltage (VG,SOA), then conducting tests with increasing short-circuit pulse lengths. After each test, acquired waveforms are analyzed, and if limits are violated, the data is stored for SCSOA determination. If limits aren't met, the experiment continues with longer pulse lengths. This approach requires a pass/fail evaluation after each test, helping to prevent short-circuit failures in SiC MOSFETs.
Figure 3: 1.2 kV/ 180 A SiC MOSFET where the short circuit current limit is 1.5 kA.
The proposed system uses the negative relationship between short circuit current and junction temperature. By defining a maximum allowable junction temperature during short circuit events, a safe drain current level can be determined. Tests demonstrate the effectiveness of this method across various DC-link voltages, ensuring safe operation without exceeding predefined current limits. The strategy involves limiting the short circuit pulse duration to prevent thermal runaway and gate drivers must react swiftly, especially at higher DC-link voltages. Figure 3 shows the effectiveness of the short circuit when the system was tested.
